A 14b 200MS/s DAC with SFDR>78dBc, IM3
نویسندگان
چکیده
A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented. Compared to traditional static-mismatch mapping and dynamic element matching, DMM reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty. This 0.14μm CMOS DAC achieves a state-of-the-art performance of SFDR>78dBc, IM3<-83dBc and NSD<-163dBm/Hz across the whole Nyquist band.
منابع مشابه
A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist
A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 1...
متن کاملA 12 bit 2.9 GS/s DAC With IM3 60 dBc Beyond 1 GHz in 65 nm CMOS
A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an dBc beyond 1 GHz while driving a 50 load with an output swing of 2.5 and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previo...
متن کاملAn 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS
This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ∆Σ DAC in 65 nm CMOS for the 60-GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output resulting in a predominantly digital DAC with only fifteen analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing w...
متن کاملA 6-bit, 500-MS/s current-steering DAC in SiGe BiCMOS technology and considerations for SFDR performance
This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises the spurious free dynamic range (SFDR) performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect. A novel current source cell is implemented that comprises heterojunction bipolar transistor current switches, negative-ch...
متن کاملDesign and Analysis of High Speed Capacitive Pipeline DACs
Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by th...
متن کامل